For the realization of this laboratory a code was generated in VHDL; In this, an ALU (the arithmetic logic unit) is performed, which has two 4-bit vector inputs and a 4-bit output with a three-bit selection input with which we can generate the six operations necessary to comply with the laboratory, three arithmetic (addition, subtraction and multiplication) and three logics (and, xor and xnor).
For the ALU code, signals are created to handle the data input and output vectors and a case statement to select each operation, syntax is reviewed, a schematic is created and the symbol is added. In addition, a memory of six registers is created in VHDL which can be organized according to the order of its operations, the syntax is reviewed and the symbol interconnected with the selection input of the ALU is created.

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